1. Technical Field
The present invention relates to a plasma display device and a driving method thereof and, in particular, to a power recovery circuit of a plasma display device.
2. Related Art
Plasma display devices are flat panel displays that use plasma generated by gas discharge to display characters or images. The plasma display devices include, according to their size, more than several tens to millions of pixels arranged in the form of a matrix. These plasma display devices are classified into a direct current (DC) type and an alternating current (AC) type according to patterns of waveforms of driving voltages applied thereto and discharge cell structures thereof.
An AC plasma display panel (PDP) has scan electrodes and sustain electrodes in parallel on one side thereof, and has address electrodes crossing the scan electrodes and sustain electrodes on another side thereof. The sustain electrodes are formed to correspond to the respective scan electrodes, one terminal of each being coupled in common. In general, a method for driving the AC plasma display panel can be expressed in terms of temporal operation periods, i.e., a reset period, an address period, and a sustain period.
The reset period is a period in which the state of each cell is reset such that an addressing operation of each cell is smoothly performed, and the address period is a period in which an address voltage is applied to an addressed call in order to accumulate wall charge on the addressed cell so as to select a cell to be turned on and a cell not to be turned on in the plasma display panel (PDP). The sustain period is a period in which sustain discharge voltage pulses are applied to the addressed cell, thereby causing a discharge according to which a picture is actually displayed.
Since there is a discharge space between a scan electrode and a sustain electrode, and since there is a discharge space between a surface on which an address electrode is formed and a surface on which scan and sustain electrodes are formed, these spaces operate as capacitive loads (referred to as panel capacitors hereinafter), and capacitance exists on the panel. Hence, charge-injecting reactive power for generating a predetermined voltage for the capacitance is needed, in addition to power for a sustain discharge in order to apply waveforms for the sustain discharge. Therefore, a sustain discharge circuit includes a power recovery circuit for recovering the reactive power and re-using the same, such power recovery circuits being disclosed by L. F. Weber in U.S. Pat. Nos. 4,866,349 and 5,081,400. The power recovery circuits of Weber fail to recover 100% of the reactive power because of loss caused by switching in the power recovery circuits, and it is accordingly difficult to increase the sustain discharge voltage to the voltage of Vs or decrease the same to 0V. When a switch for supplying the voltage of Vs or 0V is turned on, the switch performs hard switching to thus generate a switching loss and an EMI. Furthermore, the time for applying the sustain discharge pulse in the reset period or the address period is short since the time for increasing the sustain discharge pulse from 0V to Vs, and the time for decreasing the same from Vs to 0V, are long.
The information disclosed above is only for the purpose of enhancing understanding of the background of the invention, and therefore, unless explicitly described to the contrary, it should not be taken as an acknowledgment, or any form of suggestion, that this information forms the prior art that is already known to a person of ordinary skill in the art.